Category: Uncategorized

In this post we will go over the implementation of a mono delay effect for our FPGA Audio Processor.

In this post we will take our first steps into the world of floating-point audio processing with FPGAs by converting our fixed-point audio samples to floating point and performing a basic delay operation.

In this post we will create a gitignore file that matches our recommended file and directory structure for using revision control with Vivado projects.

In this post we will go over several guidelines for using revision control with Vivado projects. We will focus on block-design-, hdl- and IP-based designs using the Project Flow.

In the fourth and final part of this series we will instantiate our dBFS Converter HLS IP core in the LED Meter module. We will also run RTL simulation in Vivado and will generate the new bitstream for our Audio Processor.

In this post we will run C Synthesis and Co-Simulation for our dBFS Converter module. We will also discuss how to export the dBFS Converter from Vitis HLS and make it available for our Zynq Audio Processor project in Vivado.

In this post we will examine in detail the input files required for a Vitis HLS project and will run the C Simulation for our dBFS Converter module.

In this series we will use Vitis HLS to convert the linear values of our audio samples to the decibel scale used in digital audio processing, dBFS. In the first post we discuss how to convert our audio sample values from the linear scale to dBFS and take our first steps with Vitis HLS.

In this post we will go over a SystemVerilog testbench that can read a WAVE file and use it as input when simulating our Audio Processor.

In this post we will go over the implementation of a SystemVerilog monitor controller for our ZedBoard Audio Processor.