Category: Uncategorized

In this post we expand our Vivado Non-Project Mode Build script to include programming the generated bitstream onto the FPGA in batch mode.

In this post, the second in our recurring ‘Paying Off Technical Debt’ series, we will clean up our FPGA Audio Processor design and add support for Vivado’s non-project mode workflow.

In this post, the second of a two-part series on the FPGA implementation of a floating-point FIR filter, we add support for stereo processing to our filter and listen to a processed audio sample.

In this post we will discuss the pros and cons of fixed- and floating-point arithmetic in FPGAs and provide links to several interesting resources on this topic.

In this post, the first of a two-part series, we will implement and simulate an RTL floating-point FIR filter for our FPGA Audio Processor.

In this post we will convert the convert the pure RTL description of our FPGA Audio Processor into a Block Design to be used with the Vivado IP Integrator.

In this post, the last of a three-part series exploring dynamic range control of audio signals with a limiter, we add lookahead support to our Floating-Point FPGA Limiter module.

In this post, the second of a series on a floating-point FPGA limiter, we add support for stereo processing to our Limiter module and analyze its output by listening to a drum loop limited in our FPGA Audio Processor.

In this post we start a series in which we will explore the RTL description and simulation of a floating-point Limiter for our FPGA Audio Processor.

In this post, the second installment of a two-part series, we will explore how to run a standalone simulation in Vivado using Xilinx IP cores.